CST 334 Week 4

 

WELCOME TO WEEK 4

Learning Journal

This week we learned about Paging, a different approach that chops up space into fixed-sized pieces. This approach divides the address space into fixed-sized units, which we call a page. The physical memory in the fixed-sized slots is called page frames. These page frames contain a single virtual memory page. There are two problems with this approach: sometimes it can run slow, and it can also take up a lot of memory. A solution to these problems is the use of TLBs (Translation Lookaside Buffers), which create faster address translations. TLBs can be managed by both the OS and the hardware. There are TLB misses and TLB hits. When there is a TLB hit, it means that the TLB holds the translation. However, when there is a TLB miss, the CPU does not find the translation in the TLB.

We were also introduced to solutions to the problem of page tables being too big, consuming a lot of memory. Some of the approaches are the hybrid approach (which consists of segmentation and paging), multilevel page tables, and inverted page tables. We also learned about physical memory mechanisms and policies. Some of the policies mentioned were the Optimal policy, a simple policy (FIFO), Random, and LRU (Least Recently Used). Each of these has its pros and cons. For example, the simple policy places the pages in a queue when they enter the system. When replacement occurs, the first-in page is evicted. The advantage of this policy is that it is easy to implement. However, the disadvantage is that it is unable to determine the importance of blocks.